FPGA学习笔记1-LED流水灯

//  2017/7/19     meisq          1.0         Original
//*******************************************************************************/

`timescale 1ns / 1ps               // set up timescale as 1ns
module led_test                    // config the module,input output reg included
(
	input           clk,           // system clock 50Mhz on board
	input           rst_n,         // reset ,low active
	output          led1,          // led on core board
	output reg[3:0] led            // LED,use for control the LED signal on expansion board
);

assign led1 = led[0];

//define the time counter
reg [31:0]      timer;

// cycle counter:from 0 to 4 sec
always@(posedge clk or negedge rst_n)
begin
	if (rst_n == 1'b0)
		timer <= 32'd0;                     //when the reset signal valid,time counter clearing
	else if (timer == 32'd199_999_99)      //4 seconds count(50M*4-1=199999999)
		timer <= 32'd0;                     //count done,clearing the time counter
	else
		timer <= timer + 32'd1;             //timer counter = timer counter + 1
end

// LED control
always@(posedge clk or negedge rst_n)
begin
	if (rst_n == 1'b0)
		led <= 4'b0000;                     //when the reset signal active
	else if (timer == 32'd49_999_99)       //time counter count to 1st sec,LED1 lighten
		led <= 4'b0001;
	else if (timer == 32'd99_999_99)       //time counter count to 2nd sec,LED2 lighten
		led <= 4'b0011;
	else if (timer == 32'd149_999_99)      //time counter count to 3rd sec,LED3 lighten
		led <= 4'b0111;
	else if (timer == 32'd199_999_99)      //time counter count to 4th sec,LED4 lighten
		led <= 4'b1111;
end
endmodule

 

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